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INTEGRATED CIRCUITS
DATA SHEET
PCF2113X LCD controllers/drivers
Product specification Supersedes data of 1997 Apr 04 File under Integrated Circuits, IC12 2001 Dec 19
Philips Semiconductors
Product specification
LCD controllers/drivers
CONTENTS 1 1.1 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 9 9.1 9.2 9.3 9.4 FEATURES Note APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION LCD supply voltage generator LCD bias voltage generator Oscillator External clock Power-on reset Power-down mode Registers Busy flag Address Counter (AC) Display Data RAM (DDRAM) Character Generator ROM (CGROM) Character Generator RAM (CGRAM) Cursor control circuit Timing generator LCD row and column drivers Reset function INSTRUCTIONS Clear display Return home Entry mode set Display control (and partial Power-down mode) Cursor or display shift Function set Set CGRAM address Set DDRAM address Read busy flag and read address Write data to CGRAM or DDRAM Read data from CGRAM or DDRAM EXTENDED FUNCTION SET INSTRUCTIONS AND FEATURES New instructions Icon control Bit IM Bit IB 9.5 9.6 9.7 9.8 9.9 9.10 9.11 10 10.1 10.2 11 12 13 14 15 16 16.1 16.2 16.3 16.4 16.5 17 18 19 20 20.1 20.2 20.3 20.4 20.5 21 22 23 24 25
PCF2113X
Direct mode Voltage multiplier control Screen configuration Display configuration Temperature control Set VLCD Reducing current consumption INTERFACES TO MICROCONTROLLER Parallel interface I2C-bus interface LIMITING VALUES HANDLING INSTRUCTIONS DC CHARACTERISTICS AC CHARACTERISTICS DEVICE PROTECTION CIRCUITS APPLICATION INFORMATION General application information 4-bit operation, 1-line display using internal reset 8-bit operation, 1-line display using internal reset 8-bit operation, 2-line display I2C-bus operation, 1-line display BONDING PAD INFORMATION TRAY INFORMATION PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS BARE DIE DISCLAIMER PURCHASE OF PHILIPS I2C COMPONENTS
2001 Dec 19
2
Philips Semiconductors
Product specification
LCD controllers/drivers
1 FEATURES
PCF2113X
* Single-chip LCD controller/driver * 2-line display of up to 12 characters + 120 icons, or 1-line display of up to 24 characters + 120 icons * 5 x 7 character format plus cursor; 5 x 8 for kana (Japanese) and user defined symbols * Icon mode: reduced current consumption while displaying * Icon blink function * On-chip: - Configurable 4, 3 or 2 voltage multiplier generating LCD supply voltage, independent of VDD, programmable by instruction (external supply also possible) - Temperature compensation of on-chip generated VLCD: -0.16 to -0.24 %/K (programmable by instruction) - Generation of intermediate LCD bias voltages - Oscillator requires no external components (external clock also possible). * Display data RAM: 80 characters * Character generator ROM: 240, 5 x 8 characters * Character generator RAM: 16, 5 x 8 characters; 3 characters used to drive 120 icons, 6 characters used if icon blink feature is used in application * 4 or 8-bit parallel bus and 2-wire I2C-bus interface * CMOS compatible * 18 row and 60 column outputs * Multiplex rates 1 : 18 (for normal operation), 1 : 9 (for single line operation) and 1 : 2 (for icon only mode) * Uses common 11 code instruction set (extended) * Logic supply voltage range VDD1 - VSS1 = 1.8 to 5.5 V (chip may be driven with two battery cells) * VLCD generator supply voltage range VDD2 - VSS2 = 2.2 to 4.0 V * Display supply voltage range VLCD - VSS2 = 2.2 to 6.5 V * Direct mode to save current consumption for icon mode and Mux 1 : 9 (depending on VDD2 value and LCD liquid properties) * Very low current consumption (20 to 200 A): - Icon mode: <25 A - Power-down mode: <2 A. 3 GENERAL DESCRIPTION 1.1 Note Icon mode is used to save current. When only icons are displayed, a much lower operating voltage VLCD can be used and the switching frequency of the LCD outputs is reduced. In most applications it is possible to use VDD as VLCD. 2 APPLICATIONS
* Telecom equipment * Portable instruments * Point-of-sale terminals.
The PCF2113X is a low power CMOS LCD controller and driver, designed to drive a dot matrix LCD display of 2-line by 12 or 1-line by 24 characters with 5 x 8 dot format. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD bias voltages, resulting in a minimum of external components and lower system current consumption. The PCF2113X interfaces to most microcontrollers via a 4 or 8-bit bus or via the 2-wire I2C-bus. The chip contains a character generator and displays alphanumeric and kana (Japanese) characters. The letter `x' in PCF2113X characterizes the built-in character set. Various character sets can be manufactured on request.
2001 Dec 19
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Philips Semiconductors
Product specification
LCD controllers/drivers
4 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME PCF2113AU/10/F4 PCF2113DU/10/F4 PCF2113DU/F4 PCF2113DH/F4 PCF2113DU/2/F4 PCF2113EU/2/F4 PCF2113WU/2/F4 - - - LQFP100 - - - DESCRIPTION chip on flexible film carrier chip on flexible film carrier chip in tray plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm chip with bumps in tray chip with bumps in tray chip with bumps in tray
PCF2113X
VERSION - - - SOT407-1 - - -
2001 Dec 19
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Philips Semiconductors
Product specification
LCD controllers/drivers
5 BLOCK DIAGRAM
PCF2113X
handbook, full pagewidth
C1 to C60
R1 to R18
60 BIAS VOLTAGE GENERATOR COLUMN DRIVERS 60 DATA LATCHES VLCDSENSE VLCD2 VLCD GENERATOR 60 SHIFT REGISTER 5 x 12 BIT 5 CURSOR AND DATA CONTROL 5 VDD1 VDD2 VDD3 VSS1 VSS2 8 CHARACTER GENERATOR RAM (128 x 5) (CGRAM) 16 CHARACTERS CHARACTER GENERATOR ROM (CGROM) 240 CHARACTERS
18 ROW DRIVERS 18 SHIFT REGISTER 18-BIT
VLCD1
OSCILLATOR
OSC
TIMING GENERATOR
T1
7
DISPLAY DATA RAM (DDRAM) 80 CHARACTERS/BYTES 7 ADDRESS COUNTER (AC) 7 7 INSTRUCTION DECODER 7 DISPLAY ADDRESS COUNTER
PD
T2 T3
PCF2113X
DATA REGISTER (DR) 8 I/O BUFFER 8 BUSY FLAG INSTRUCTION REGISTER(IR) 8 POWER-ON RESET
DB0 to DB3/SA0
DB4 to DB7
E
R/W
RS
SCL
SDA
MGE990
Fig.1 Block diagram.
2001 Dec 19
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Philips Semiconductors
Product specification
LCD controllers/drivers
6 PINNING SYMBOL VDD1 OSC PD T3 T1 T2 VSS1 VSS2 VLCD2 VLCDSENSE VLCD1 R9 to R16 R18 C60 to C53 dummy pad dummy pad C52 to C28 dummy pad dummy pad C27 to C3 dummy pad dummy pad C2 C1 R8 to R1 R17 SCL SDA E RS R/W DB7 DB6 DB5 DB4 DB3/SA0 DB2 DB1 2001 Dec 19 PIN PCF2113DH 1 2 3 - 4 - 5 6 7 - 8 9 to 16 17 18 to 25 - - 26 to 50 - - 51 to 75 - - 76 77 78 to 85 86 87 88 89 90 91 92 93 94 95 96 97 98 PAD(1) PCF2113XU 1 2 3 4 5 6 7 8 9 10 11 12 to 19 20 21 to 28 29 30 31 to 55 56 57 58 to 82 83 84 85 86 87 to 94 95 96 97 98 99 100 101 102 103 104 105 106 107 TYPE P I I I I I P P O I I O O O - - O - - O - - O O O O I I/O I I I I/O I/O I/O I/O I/O I/O I/O LCD column driver output 2 LCD column driver output 1 LCD row driver outputs 8 to 1 LCD row driver output 17 I2C-bus serial clock input; note 4 I2C-bus serial data input/output; note 4 data bus clock input; note 4 register select input read/write input 8-bit bidirectional data bus bit 7; note 5 8-bit bidirectional data bus bit 6 8-bit bidirectional data bus bit 5 8-bit bidirectional data bus bit 4 LCD column driver outputs 27 to 3 LCD column driver outputs 52 to 28 DESCRIPTION
PCF2113X
supply voltage 1 for all except VLCD generator oscillator/external clock input; note 2 power-down select input; for normal operation PD is LOW test pad; open circuit and not user accessible test pin; must be connected to VSS1 test pad; must be connected to VSS1 ground 1 for all except VLCD generator ground 2 for VLCD generator VLCD output if VLCD is generated internally; note 7 input (VLCD) for voltage multiplier regulation; notes 3 and 7 input for generation of LCD bias levels; note 7 LCD row driver outputs 9 to 16 LCD row driver output 18 LCD column driver outputs 60 to 53
8-bit bidirectional data bus bit 3 or I2C-bus address pin; notes 4 and 5 8-bit bidirectional data bus bit 2 8-bit bidirectional data bus bit 1 6
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2113X
SYMBOL DB0 VDD2 VDD3 Notes
PIN PCF2113DH 99 100 -
PAD(1) PCF2113XU 108 109 110
TYPE I/O P P
DESCRIPTION 8-bit bidirectional data bus bit 0 supply voltage 2 for VLCD generator; note 6 supply voltage 3 for VLCD generator; notes 3 and 6
1. Bonding pad location information is given in Chapter 17. 2. When the on-chip oscillator is used this pad must be connected to VDD1. 3. In the LQFP100 version this signal is connected internally and can not be accessed at any pin. 4. When the I2C-bus is used, the parallel interface pin E must be LOW. In the I2C-bus read mode DB7 to DB0 should be connected to VDD1 or left open-circuit. When the parallel bus is used, the pins SCL and SDA must be connected to VSS1 or VDD1; they must not be left open-circuit. When the 4-bit interface is used without reading out from the PCF2113X (R/W is set permanently to logic 0), the unused ports DB0 to DB4 can either be set to VSS1 or VDD1 instead of leaving them open-circuit. 5. DB7 may be used as the busy flag, signalling that internal operations are not yet completed. In 4-bit operations the four higher order lines DB7 to DB4 are used; DB3 to DB0 must be left open-circuit except for I2C-bus operations (see note 4). 6. VDD2 and VDD3 should always be equal. 7. When VLCD is generated internally, pins VLCD1, VLCD2 and VLCDSENSE must be connected together. When external VLCD is supplied, pin VLCD2 should be left open-circuit to avoid any stray current, pins VLCD1 and VLCDSENSE must be connected together.
2001 Dec 19
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2113X
handbook, full pagewidth
100 VDD2
96 DB3/SA0
88 SDA
99 DB0
98 DB1
97 DB2
95 DB4
94 DB5
93 DB6
92 DB7
87 SCL
91 R/W
86 R17
90 RS
85 R1
84 R2
83 R3
82 R4
81 R5
80 R6
79 R7
78 R8
77 C1
VDD1 OSC PD T1 VSS1 VSS2 VLCD2 VLCD1 R9
1 2 3 4 5 6 7 8 9
76 C2 75 C3 74 C4 73 C5 72 C6 71 C7 70 C8 69 C9 68 C10 67 C11 66 C12 65 C13 64 C14 63 C15 62 C16 61 C17 60 C18 59 C19 58 C20 57 C21 56 C22 55 C23 54 C24 53 C25 52 C26 51 C27 C28 50
R10 10 R11 11 R12 12 R13 13 R14 14 R15 15 R16 16 R18 17 C60 18 C59 19 C58 20 C57 21 C56 22 C55 23 C54 24 C53 25 C52 26 C51 27 C50 28 C49 29 C48 30 C47 31 C46 32 C45 33 C44 34 C43 35 C42 36 C41 37 C40 38 C39 39 C38 40 C37 41 C36 42 C35 43 C34 44 C33 45 C32 46 C31 47 C30 48 C29 49
PCF2113X
89 E
MGE989
Fig.2 Pin configuration (LQFP100).
2001 Dec 19
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Philips Semiconductors
Product specification
LCD controllers/drivers
7 7.1 FUNCTIONAL DESCRIPTION LCD supply voltage generator
PCF2113X
The generated VLCD is independent of VDD and is temperature compensated. When the VLCD generator and the direct mode are switched off, an external voltage may be supplied at connected pins VLCD1 and VLCD2. VLCD1 and VLCD2 may be higher or lower than VDD2. During direct mode (program DM register bit) the internal VLCD generator is turned off and the VLCD2 output voltage is directly connected to VDD2. This reduces the current consumption during icon mode and Mux 1 : 9 (depending on VDD2 value and LCD liquid properties). The VLCD generator ensures that, as long as VDD is in the valid range (2.2 to 4 V), the required peak voltage VOP = 6.5 V can be generated at any time. 7.2 LCD bias voltage generator
The LCD supply voltage may be generated on-chip. The VLCD generator is controlled by two internal 6-bit registers: VA and VB. The nominal LCD operating voltage at room temperature is given by the relationship: VOP(nom) = (integer value of register x 0.08) + 1.82 7.1.1 PROGRAMMING RANGES
Programmed value: 1 to 63. Voltage: 1.90 to 6.86 V. Tref = 27 C. Values producing more than 6.5 V at operating temperature are not allowed. Operation above this voltage may damage the device. When programming the operating voltage the VLCD tolerance and temperature coefficient must be taken into account. Values below 2.2 V are below the specified operating range of the chip and are therefore not allowed. Value 0 for VA and VB switches the generator off (i.e. VA = 0 in character mode, VB = 0 in icon mode). Usually register VA is programmed with the voltage for character mode and register VB with the voltage for icon mode. When VLCD is generated on-chip the VLCD pins should be decoupled to VSS with a suitable capacitor. Table 1 Bias levels as a function of multiplex rate; note 1 V1 VLCD VLCD VLCD V2
3/ 4 3/ 4 2/ 3
The intermediate bias voltages for the LCD display are also generated on-chip. This removes the need for an external resistive bias chain and significantly reduces the system current consumption. The optimum value of VLCD depends on the multiplex rate, the LCD threshold voltage (Vth) and the number of bias levels. Using a 5-level bias scheme for 1 : 18 maximum rate allows VLCD < 5 V for most LCD liquids. The intermediate bias levels for the different multiplex rates are shown in Table 1. These bias levels are automatically set to the given values when switching to the corresponding multiplex rate.
MULTIPLEX NUMBER RATE OF LEVELS 1 : 18 1:9 1:2 Note 5 5 4
V3
1/ 2 1/ 2 2/ 3
V4
1/ 2 1/ 2 1/ 3
V5
1/ 4 1/ 4 1/ 3
V6 VSS VSS VSS
1. The values in the table are given relative to VLCD - VSS, e.g. 3/4 means 3/4 x (VLCD - VSS).
2001 Dec 19
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Philips Semiconductors
Product specification
LCD controllers/drivers
7.3 Oscillator
PCF2113X
The data register temporarily stores data to be read from the DDRAM and CGRAM. When reading, data from the DDRAM or CGRAM corresponding to the address in the instruction register is written to the data register prior to being read by the `read data' instruction. 7.8 Busy flag
The on-chip oscillator provides the clock signal for the display system. No external components are required and the OSC pin must be connected to VDD1. 7.4 External clock
If an external clock is to be used this input is at the OSC pin. The resulting display frame frequency is given by: f OSC f frame = ------------3 072 Only in the Power-down mode is the clock allowed to be stopped (OSC connected to VSS), otherwise the LCD is frozen in a DC state. 7.5 Power-on reset
The busy flag indicates the internal status of the PCF2113X. A logic 1 indicates that the chip is busy and further instructions will not be accepted. The busy flag is output to pin DB7 when bit RS = 0 and bit R/W = 1. Instructions should only be written after checking that the busy flag is at logic 0 or waiting for the required number of cycles. 7.9 Address Counter (AC)
The on-chip Power-on reset block initializes the chip after power-on or power failure. This is a synchronous reset and requires 3 oscillator cycles to be executed. 7.6 Power-down mode
The chip can be put into Power-down mode by applying an external active HIGH level to the PD pin. In Power-down mode all static currents are switched off (no internal oscillator, no bias level generation and all LCD outputs are internally connected to VSS). During power-down, information in the RAMs and the chip state are preserved. Instruction execution during power-down is possible when pin OSC is externally clocked. 7.7 Registers
The address counter assigns addresses to the DDRAM and CGRAM for reading and writing and is set by the commands `set CGRAM address' and `set DDRAM address'. After a read/write operation the address counter is automatically incremented or decremented by 1. The address counter contents are output to the bus (DB6 to DB0) when bit RS = 0 and bit R/W = 1. 7.10 Display Data RAM (DDRAM)
The PCF2113X has two 8-bit registers, an Instruction Register (IR) and a Data Register (DR). The Register Select (RS) signal determines which register will be accessed. The instruction register stores instruction codes such as `display clear', `cursor shift', and address information for the Display Data RAM (DDRAM) and Character Generator RAM (CGRAM).The instruction register can be written to but not read from by the system controller. Table 2 Address space and wrap-around operation MODE Address space Read/write wrap-around (moves to next line) Display shift wrap-around (stays within line)
The DDRAM stores up to 80 characters of display data represented by 8-bit character codes. RAM locations which are not used for storing display data can be used as general purpose RAM. The basic RAM to display addressing scheme is shown in Fig.3. With no display shift the characters represented by the codes in the first 24 RAM locations starting at address 00H in line 1 are displayed. Figures 4 and 5 show the display mapping for right and left shift respectively. When data is written to or read from the DDRAM, wrap-around occurs from the end of one line to the start of the next line. When the display is shifted each line wraps around within itself, independently of the others. Thus all lines are shifted and wrapped around together. The address ranges and wrap-around operations for the various modes are shown in Table 2.
1 x 24 00 to 4F 4F to 00 4F to 00
2 x 12 00 to 27; 40 to 67 27 to 40; 67 to 00 27 to 00; 67 to 40
1 x 12 00 to 27 27 to 00 27 to 00
2001 Dec 19
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2113X
handbook, full pagewidth
display position DDRAM address
non-displayed DDRAM addresses 12345
00 01 02 03 04
22 23 24
15 16 17 18 19 4C 4D 4E 4F
1-line display non-displayed DDRAM address 12345
00 01 02 03 04
10 11 12
09 0A 0B 0C 0D 24 25 26 27
line 1
DDRAM address
12345
40 41 42 43 44
10 11 12
49 4A 4B 4C 4D 64 65 66 67
MGE991
line 2
2-line display
Fig.3 DDRAM to display mapping; no shift.
display handbook, halfpage position DDRAM address
1
23
4
5
22 23 24
14 15 16
4F 00 01 02 03
1-line display 1 DDRAM address 23 4 5 10 11 12
08 09 0A
27 00 01 02 03
line 1
1
23
4
5
10 11 12
48 49 4A
MGE992
67 40 41 42 43
line 2
2-line display
Fig.4 DDRAM to display mapping; right shift.
display handbook, halfpage position DDRAM address
1
23
4
5
22 23 24
16 17 18
01 02 03 04 05
1-line display 1 DDRAM address 23 4 5 10 11 12
0A 0B 0C
01 02 03 04 05
line 1
1
23
4
5
10 11 12
4A 4B 4C
MGE993
41 42 43 44 45
line 2
2-line display
Fig.5 DDRAM to display mapping; left shift.
2001 Dec 19
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Philips Semiconductors
Product specification
LCD controllers/drivers
7.11 Character Generator ROM (CGROM) 7.14 Timing generator
PCF2113X
The CGROM generates 240 character patterns in a 5 x 8 dot format from 8-bit character codes. Figures 7, 8, 9 and 10 show the character sets that are currently implemented. 7.12 Character Generator RAM (CGRAM)
The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not disturbed by operations on the data buses. 7.15 LCD row and column drivers
Up to 16 user defined characters may be stored in the CGRAM. Some CGRAM characters (see Fig.16) are also used to drive icons (6 if icons blink and both icon rows are used in the application; 3 if no blink but both icon rows are used in the application; 0 if no icons are driven by the icon rows). The CGROM and CGRAM use a common address space, of which the first column is reserved for the CGRAM (see Fig.7). Figure 11 shows the addressing principle for the CGRAM. 7.13 Cursor control circuit
The PCF2113X contains 18 row and 60 column drivers, which connect the appropriate LCD bias voltages in sequence to the display in accordance with the data to be displayed. R17 and R18 drive the icon rows. The bias voltages and the timing are selected automatically when the number of lines in the display is selected. Figures 12, 13, 14 and 15 show typical waveforms. Unused outputs should be left unconnected.
The cursor control circuit generates the cursor underline and/or cursor blink as shown in Fig.6 at the DDRAM address contained in the address counter. When the address counter contains the CGRAM address the cursor will be inhibited.
cursor 5 x 7 dot character font alternating display
MGA801
cursor display example
blink display example
Fig.6 Cursor and blink display examples.
2001 Dec 19
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2113X
handbook, full pagewidth upper
lower 4 bits xxxx
4 bits
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
MGE994
Fig.7 Character set `A' in CGROM.
2001 Dec 19
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2113X
handbook, full pagewidth upper
lower 4 bits xxxx
4 bits
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
MGD688
Fig.8 Character set `D' in CGROM.
2001 Dec 19
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2113X
handbook, full pagewidth upper
lower 4 bits xxxx
4 bits
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
MGD689
Fig.9 Character set `E' in CGROM.
2001 Dec 19
15
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2113X
handbook, full pagewidth upper
lower 4 bits xxxx
4 bits
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
MGU204
Fig.10 Character set `W' in CGROM.
2001 Dec 19
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2113X
character handbook, full pagewidth codes (DDRAM data) 7 6 5 4 3 2 1 lower order bits 0 0 0 0 0 0 0 6 5
CGRAM address 4 3 2 1 lower order bits 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 higher order bits
character patterns (CGRAM data) 4 3 2 1 0 4
character code (CGRAM data) 3 2 1 0
higher order bits 0 0 0
higher order bits 0 0
lower order bits 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 character pattern example 2 0 0 0 0 character pattern example 1 cursor position 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 0 1 0 0 1 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 1 1 0 0 0 0 0 1 1 1 1 1 0 1 0 0 1 0 1 0 0 0 1 1 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 0 0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
MGE995
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
0 0 1 1
0 1 0 1
Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6. CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and display is performed by logical OR with the cursor. Data in the 8th position will appear in the cursor position. Character pattern column positions correspond to CGRAM data bits 0 to 4, as shown in this figure. As shown in Figs 7 and 8, CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data = logic 1 corresponds to selection for display. Only bits 0 to 5 of the CGRAM address are set by the `set CGRAM address' command. Bit 6 can be set using the `set DDRAM address' command in the valid address range or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the `read busy flag' and `address counter' command.
Fig.11 Relationship between CGRAM addresses, data and display patterns.
2001 Dec 19
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2113X
handbook, full pagewidth
frame n
frame n + 1
state 1 (ON) state 2 (OFF)
R1 R2 R3 R4 R5
ROW 1
VLCD V2 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VOP
R6 R7 R8 R9
ROW 9
ROW 2
COL1
COL2
0.5VOP 0.25VOP state 1 0 V -0.25VOP -0.5VOP -VOP VOP 0.5VOP 0.25VOP state 2 0 V -0.25VOP -0.5VOP -VOP
MGE996
123
18 1 2 3
18
Fig.12 MUX 1 : 18 LCD waveforms; character mode.
2001 Dec 19
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2113X
handbook, full pagewidth
frame n
frame n + 1
state 1 (ON) state 2 (OFF)
R1 R2 R3 R4 R5
ROW 1
VLCD V2 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VOP
R6 R7 R8 R9
ROW 2
ROW 3
COL1
COL2
0.5VOP 0.25VOP state 1 0 V -0.25VOP -0.5VOP -VOP VOP 0.5VOP 0.25VOP state 2 0 V -0.25VOP -0.5VOP -VOP
1 2 3 9 1 2 3 9
MGU217
R10 to R18 to be left open.
Fig.13 MUX 1 : 9 LCD waveforms; character mode.
2001 Dec 19
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2113X
handbook, full pagewidth
frame n
frame n + 1 only icons are driven (MUX 1 : 2)
VLCD ROW 17 2/3 1/3 VSS
VLCD ROW 18 2/3 1/3 VSS
VLCD ROW 1 to 16 2/3 1/3 VSS
VLCD COL 1 ON/OFF 2/3 1/3 VSS
VLCD COL 2 OFF/ON 2/3 1/3 VSS
VLCD COL 3 ON/ON 2/3 1/3 VSS
VLCD COL 4 OFF/OFF 2/3 1/3 VSS
MGE997
Fig.14 MUX 1 : 2 LCD waveforms; icon mode.
2001 Dec 19
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2113X
handbook, full pagewidth V PIXEL
frame n
frame n + 1 state 1 (ON)
state 1 COL 1 ROW 17
VOP 2/3 VOP 1/3 VOP 0 -1/3 VOP -2/3 VOP -VOP VOP 2/3 VOP 1/3 VOP 0 -1/3 VOP -2/3 VOP -VOP VOP 2/3 VOP 1/3 VOP
state 2 (OFF)
R17 R18 R1-16
state 3 (OFF)
state 2 COL 2 ROW 17
state 3 COL 1 0 ROW 1 to 16 -1/3 VOP -2/3 VOP -VOP
MGE998
VON(rms) = 0.745VOP VOFF(rms) = 0.333VOP V ON D = ------------- = 2.23 V OFF
Fig.15 MUX 1 : 2 LCD waveforms; icon mode.
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Philips Semiconductors
Product specification
LCD controllers/drivers
7.16 Reset function
PCF2113X
The PCF2113X automatically initializes (resets) when power is turned on. The chip executes a reset sequence, including a `clear display', requiring 165 oscillator cycles. After the reset the chip has the state shown in Table 3. Table 3 State after reset FUNCTION clear display entry mode set display control I/D = 1 S=0 3 D=0 C=0 B=0 4 function set DL = 1 M=0 H=0 SL = 0 5 +1 (increment) no shift display off cursor off cursor character blink off 8-bit interface 1-line display normal instruction set MUX 1 : 18 mode CONTROL BIT STATE CONDITIONS
STEP 1 2
default address pointer to DDRAM; the Busy Flag (BF) indicates the busy state (BF = 1) until initialization ends; the busy state lasts 2 ms; the chip may also be initialized by software; see Tables 17 and 18 icon control display/screen configuration VLCD temperature coefficient set VLCD I2C-bus interface reset S1 = 1; S0 = 0 VLCD generator voltage multiplier set at factor 4 Set HVgen stages IM = 0; IB = 0; DM = 0 L = 0; P = 0; Q = 0 TC1 = 0; TC2 = 0 VA = 0; VB = 0 icons, icon blink and direct mode disabled default configurations default temperature coefficient VLCD generator off
6 7 8 9 10 11
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Philips Semiconductors
Product specification
LCD controllers/drivers
8 INSTRUCTIONS
PCF2113X
In normal use, category 3 instructions are used most frequently. However, automatic incrementing by 1 (or decrementing by 1) of internal RAM addresses after each data write lessens the microcontroller program load. The display shift in particular can be performed concurrently with display data write, enabling the designer to develop systems in minimum time with maximum programming efficiency. During internal operation, no instructions other than the `read busy flag' and `read address' instructions will be executed. Because the busy flag is set to a logic 1 while an instruction is being executed, check to ensure it is a logic 0 before sending the next instruction or wait for the maximum instruction execution time, as given in Table 5. An instruction sent while the busy flag is logic 1 will not be executed.
Only two PCF2113X registers, the Instruction Register (IR) and the Data Register (DR) can be directly controlled by the microcontroller. Before internal operation, control information is stored temporarily in these registers, to allow interfacing to various types of microcontrollers which operate at different speeds or to allow interface to peripheral control ICs. The instruction set for I2C-bus commands is given in Table 4. The PCF2113X operation is controlled by the instructions shown in Table 5 together with their execution time. Details are explained in subsequent sections. Instructions are of 4 types, those that: 1. Designate PCF2113X functions such as display format, data length, etcetera. 2. Set internal RAM addresses 3. Perform data transfer with internal RAM 4. Others. Table 4 Instruction set for I2C-bus commands CONTROL BYTE Co RS 0 Note 1. R/W is set together with the slave address. 0 0 0 0 0
COMMAND BYTE
I2C-BUS COMMANDS
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 note 1
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LCD controllers/drivers
INSTRUCTION H = 0 or 1 NOP Function set
RS
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DESCRIPTION
REQUIRE CLOCK CYCLES
0 0
0 0
0 0
0 0
0 1
0 DL
0 0
0 M
0 SL
0 H
no operation sets interface Data Length (DL), number of display lines (M), single line/MUX 1 : 9 (SL) and extended instruction set control (H) reads the Busy Flag (BF) indicating internal operating is being performed and reads Address counter (AC) contents reads data from CGRAM or DDRAM writes data from CGRAM or DDRAM
3 3
Read busy flag and address counter Read data Write data H=0 Clear display Return home
0
1
BF
AC
0
1 1
1 0
read data write data
3 3
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 1
1 0
clears entire display and sets DDRAM address 0 in address counter sets DDRAM address 0 in address counter; also returns shifted display to original position; DDRAM contents remain unchanged sets cursor move direction (I/D) and specifies shift of display (S); these operations are performed during data write and read sets entire display on/off (D), cursor on/off (C) and blink of cursor position character (B); D = 0 (display off) puts chip into the Power-down mode moves cursor or shifts display (S/C) to right or left (R/L) without changing DDRAM contents sets CGRAM address; bit DB6 is to be set by the command `set DDRAM address'; look at the description of the commands sets DDRAM address
165 3
Entry mode set
0
0
0
0
0
0
0
1
I/D
S
3
Display control
0
0
0
0
0
0
1
D
C
B
3
Cursor/display shift Set CGRAM address Set DDRAM address
0 0
0 0
0 0
0 1
0
1
S/C
R/L
0
0
3 3 Product specification
ACG
PCF2113X
0
0
1
ADD
3
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LCD controllers/drivers
INSTRUCTION H=1 Reserved Screen configuration Display configuration Icon control Temperature control Set HVgen stages Set VLCD
RS
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DESCRIPTION
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 1
0 0 0 0 0 1 V
0 0 0 0 0 0
0 0 0 0 1 0
0 0 0 1 0 0
0 0 1 IM 0 0
0 1 P IB
1 L Q
do not use set screen configuration (L) set display configuration, columns (P) and rows (Q)
DM set Icon Mode (IM), Icon Blink (IB), Direct Mode (DM)
TC1 TC2 set Temperature Coefficient (TCx) S1 S0 set internal VLCD generator voltage multiplier stages (S1 = 1 and S0 = 1 not allowed) store VLCD in register VA or VB (V)
voltage
PCF2113X
Philips Semiconductors
Product specification
LCD controllers/drivers
Table 6 BIT Co DL 4 bits Explanations of symbols used in Tables 4 and 5. LOGIC STATE 0 last control byte; see Table 4 8 bits 2-line by 12 display
PCF2113X
LOGIC STATE 1 another control byte follows after data/command
M (no impact, 1-line by 24 display if SL = 1) SL H I/D S D C B S/C R/L L (no impact, if M = 1 or SL = 1) P Q IM IB DM V 8.1 MUX 1 : 18 (1 x 24 or 2 x 12 character display) use basic instruction set decrement display freeze display off cursor off cursor character blink off; character at cursor position does not blink cursor move left shift left/right screen: standard connection 1st 12 characters of 24; columns are from 1 to 60
MUX 1 : 9 (1 x 12 character display) use extended instruction set increment display shift display on cursor on cursor character blink on; character at cursor position blinks display shift right shift left/right screen; mirrored connection 1st 12 characters of 24; columns are from 1 to 60
2nd 12 characters of 24; columns are from 1 to 60 2nd 12 characters of 24; columns are from 60 to 1 column data: left to right; column data is displayed column data; right to left; column data is displayed from 1 to 60 from 60 to 1 row data; top to bottom; row data is displayed from row data; bottom to top; row data is displayed 1 to 16 and icon row data is in 17 and 18 from 16 to 1 and icon row data is in 18 and 17 character mode; full display icon blink disabled direct mode disabled set VA icon mode; only icons displayed icon blink enabled direct mode enabled set VB 8.2 Return home
Clear display
`Clear display' writes character code 20H into all DDRAM addresses (the character pattern for character code 20H must be a blank pattern), sets the DDRAM address counter to logic 0 and returns the display to its original position, if it was shifted. Thus, the display disappears and the cursor or blink position goes to the left edge of the display. Sets entry mode I/D = 1 (increment mode). S of entry mode does not change. The instruction `clear display' requires extra execution time. This may be allowed by checking the Busy Flag (BF) or by waiting until the 165 clock cycles have elapsed. The latter must be applied where no read-back options are foreseen, as in some Chip-On-Glass (COG) applications.
`Return home' sets the DDRAM address counter to logic 0 and returns the display to its original position if it was shifted. DDRAM contents do not change. The cursor or blink position goes to the left of the first display line. I/D and S of entry mode do not change.
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Philips Semiconductors
Product specification
LCD controllers/drivers
8.3 8.3.1 Entry mode set BIT I/D 8.4.3 BIT B
PCF2113X
When I/D = 1 (0) the DDRAM or CGRAM address increments (decrements) by 1 when data is written into or read from the DDRAM or CGRAM. The cursor or blink position moves to the right when incremented and to the left when decremented. The cursor underline and cursor character blink are inhibited when the CGRAM is accessed. 8.3.2 BIT S
The character indicated by the cursor blinks when B = 1. The cursor character blink is displayed by switching between display characters and all dots on with a period of f OSC approximately 1 second, with f blink = ---------------52 224 The cursor underline and the cursor character blink can be set to display simultaneously. 8.5 Cursor or display shift
When S = 1, the entire display shifts either to the right (I/D = 0) or to the left (I/D = 1) during a DDRAM write. Thus it appears as if the cursor stands still and the display moves. The display does not shift when reading from the DDRAM, or when writing to or reading from the CGRAM. When S = 0, the display does not shift. 8.4 8.4.1 Display control (and partial Power-down mode) BIT D
`Cursor/display shift' moves the cursor position or the display to the right or left without writing or reading display data. This function is used to correct a character or move the cursor through the display. In 2-line displays, the cursor moves to the next line when it passes the last position (40) of the line. When the displayed data is shifted repeatedly all lines shift at the same time; displayed characters do not shift into the next line. The Address Counter (AC) content does not change if the only action performed is shift display, but increments or decrements with the `cursor display shift'. 8.6 8.6.1 Function set BIT DL (PARALLEL MODE ONLY)
The display is on when D = 1 and off when D = 0. Display data in the DDRAM is not affected and can be displayed immediately by setting D = 1. When the display is off (D = 0) the chip is in partial Power-down mode: * The LCD outputs are connected to VSS * The LCD generator and bias generator are turned off. Three oscillator cycles are required after sending the `display off' instruction to ensure all outputs are at VSS, afterwards the oscillator can be stopped. If the oscillator is running during partial Power-down mode (`display off') the chip can still execute instructions. Even lower current consumption is obtained by inhibiting the oscillator (OSC = VSS). To ensure IDD < 1 A, the parallel bus pins DB7 to DB0 should be connected to VDD; pins RS and R/W to VDD or left open-circuit and pin PD to VDD. Recovery from Power-down mode: PD back to VSS, if necessary pin OSC back to VDD and send a `display control' instruction with D = 1. 8.4.2 BIT C
Sets interface data width. Data is sent or received in bytes (DB7 to DB0) when DL = 1 or in two nibbles (DB7 to DB4) when DL = 0. When 4-bit width is selected, data is transmitted in two cycles using the parallel bus. In a 4-bit application DB3 to DB0 should be left open-circuit (internal pull-ups). Hence in the first `function set' instruction after power-on M, SL and H are set to logic 1. A second `function set' must then be sent (2 nibbles) to set M, SL and H to their required values. `Function set' from the I2C-bus interface sets the DL bit to logic 1. 8.6.2 BIT M
Selects either 1-line by 24 display (M = 0) or 2-line by 12 display (M = 1). 8.6.3 BIT SL
The cursor is displayed when C = 1 and inhibited when C = 0. Even if the cursor disappears, the display functions I/D, etcetera, remain in operation during display data write. The cursor is displayed using 5 dots in the 8th line (see Fig.6).
Selects MUX 1 : 9, 1-line by 12 display (independent of M and L). Only rows 1 to 8 and 17 are to be used. All other rows must be left open-circuit. The DDRAM map is the same as in the 2-line by 12 display mode, however, the second line cannot be displayed.
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Philips Semiconductors
Product specification
LCD controllers/drivers
8.6.4 BIT H 8.10
PCF2113X
Write data to CGRAM or DDRAM
When H = 0 the chip can be programmed via the standard 11 instruction codes used in the PCF2116 and other LCD controllers. When H = 1 the extended range of instructions will be used. These are mainly for controlling the display configuration and the icons. 8.7 Set CGRAM address
`Write data' writes binary 8-bit data DB7 to DB0 to the CGRAM or the DDRAM. Whether the CGRAM or DDRAM is to be written into is determined by the previous `set CGRAM address' or `set DDRAM address' command. After writing, the address automatically increments or decrements by 1, in accordance with the entry mode. Only bits DB4 to DB0 of CGRAM data are valid, bits DB7 to DB5 are `don't care'. 8.11 Read data from CGRAM or DDRAM
`Set CGRAM address' sets bits DB5 to 0 of the CGRAM address ACG into the address counter (binary A5 to A0). Data can then be written to or read from the CGRAM. Attention: the CGRAM address uses the same address register as the DDRAM address and consists of 7 bits (binary A6 to A0). With the `set CGRAM address' command, only bits DB5 to DB0 are set. Bit DB6 can be set using the `set DDRAM address' command first, or by using the auto-increment feature during CGRAM write. All bits DB6 to DB0 can be read using the `read busy flag' and `read address' command. When writing to the lower part of the CGRAM, ensure that bit DB6 of the address is not set (e.g. by an earlier DDRAM write or read action). 8.8 Set DDRAM address
`Read data' reads binary 8-bit data DB7 to DB0 from the CGRAM or DDRAM. The most recent `set address' command determines whether the CGRAM or DDRAM is to be read. The `read data' instruction gates the content of the Data Register (DR) to the bus while pin E is HIGH. After pin E goes LOW again, internal operation increments (or decrements) the AC and stores RAM data corresponding to the new AC into the DR. There are only three instructions that update the data register: * `Set CGRAM address' * `Set DDRAM address' * `Read data' from CGRAM or DDRAM. Other instructions (e.g. `write data', `cursor/display shift', `clear display' and `return home') do not modify the data register content. 9 9.1 EXTENDED FUNCTION SET INSTRUCTIONS AND FEATURES New instructions
`Set DDRAM address' sets the DDRAM address ADD into the address counter (binary A6 to A0). Data can then be written to or read from the DDRAM. 8.9 Read busy flag and read address
`Read busy flag and address counter' read the Busy Flag (BF) and Address Counter (AC). BF = 1 indicates that an internal operation is in progress. The next instruction will not be executed until BF = 0. It is recommended that the BF status is checked before the next write operation is executed. At the same time, the value of the address counter expressed in binary A6 to A0 is read out. The address counter is used by both CGRAM and DDRAM, and its value is determined by the previous instruction.
H = 1 sets the chip into alternate instruction set mode. 9.2 Icon control
The PCF2113X can drive up to 120 icons. See Fig.16 for CGRAM to icon mapping.
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2113X
handbook, full pagewidth
display:
COL 1 to 5
COL 6 to 10
COL 56 to 60
ROW 17 -
1
2
3
4
5
6
7
8
9
10
56
57
58
59
60
ROW 18 -
61
62
63
64
65
66
67
68
69
70
116 117 118 119 120
MGE999
block of 5 columns
icon no. handbook, full pagewidth
phase
ROW/COL 7 MSB 6
character codes 5 4 3 2 1 0 LSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 MSB 0 0 0
CGRAM address 5 4 3 2 1 0 4
CGRAM data 3 2 1 0 LSB 0 1 1 1 0 1 0 1 1 1 0 0
icon view
LSB MSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0
1-5 6-10 11-15
even even even
17/1-5 17/6-10 17/11-15
0 0 0
56-60 61-65
even even
17/56-60 18/1-5
0 0
0 0
0 0
0 0
0 0
0 0
0 0
1 1
0 0
0 0
0 0
1 1
0 1
1 0
1 0
1 1
1 1
1 0
1 0
1 0
116-120 1-5
even odd (blink)
18/56-60 17/1-5
0 0
0 0
0 0
0 0
0 0
0 1
1 0
0 0
0 0
0 1
1 0
0 0
1 0
1 0
1 0
1 0
1 0
1 0
0 0
1 0
116-120
odd (blink)
18/56-60
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
MGG001
CGRAM data bit = logic 1 turns the icon on, data bit = logic 0 turns the icon off. Data in character codes 0 to 3 define the icon state when icon blink is disabled or during the even phase when icon blink is enabled. Data in character codes 4 to 7 define the icon state during the odd phase when icon blink is enabled (not used for icons when icon blink is disabled).
Fig.16 CGRAM to icon mapping.
2001 Dec 19
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Philips Semiconductors
Product specification
LCD controllers/drivers
9.3 Bit IM
PCF2113X
When DM = 1, the chip is in direct mode. The internal VLCD generator is turned off and the VLCD2 output is directly connected to the VLCD generator supply voltage VDD2. The direct mode can be used to reduce the current consumption when the required VLCD2 output voltage is close to the VDD2 supply voltage. This can be the case in icon mode or in Mux 1:9 (depending on LCD liquid properties). 9.6 Voltage multiplier control
When IM = 0, the chip is in character mode. In the character mode characters and icons are driven (MUX 1 : 18). The VLCD generator, if used, produces the VLCD voltage programmed in register VA. When IM = 1, the chip is in icon mode. In the icon mode only the icons are driven (MUX 1 : 2) and the VLCD generator, if used, produces the VLCD voltage as programmed in register VB. Table 7 IM 0 1 9.4 Normal/icon mode operation MODE character mode icon mode Bit IB VLCD generates VA generates VB
Bits S1 and S0 A software configurable voltage multiplier is incorporated in the VLCD generator and can be set via the `Set HVgen stages' command. The voltage multiplier control can be used to reduce current consumption by disconnecting internal voltage multiplier stages, depending on the required VLCD output voltage (see Table 8). Table 8 S1 0 0 1 1 9.7 Bit L L = 0: the two halves of a split screen are connected in a standard way i.e. column 1/61, 2/62 to 60/120; default. L = 1: the two halves of a split screen are connected in a mirrored way i.e. column 1/120, 2/119 to 60/61. This allows single layer PCB or glass layout. S1 and S0 control of voltage multiplier S0 0 1 0 1 DESCRIPTION set VLCD generator stages to 1 (2 x voltage multiplier) set VLCD generator stages to 2 (3 x voltage multiplier) set VLCD generator stages to 3 (4 x voltage multiplier) do not use
Icon blink control is independent of the cursor/character blink function. When IB = 0, the icon blink is disabled. Icon data is stored in CGRAM character 0 to 2 (3 x 8 x 5 = 120 bits for 120 icons). When IB = 1, the icon blink is enabled. In this case each icon is controlled by two bits. Blink consists of two half phases (corresponding to the cursor on and off phases called even and odd phases hereafter). Icon states for the even phase are stored in CGRAM characters 0 to 2 (3 x 8 x 5 = 120 bits for 120 icons). These bits also define icon state when icon blink is not used (see Table 9). Icon states for the odd phase are stored in CGRAM character 4 to 6 (another 120 bits for the 120 icons). When icon blink is disabled CGRAM characters 4 to 6 may be used as normal CGRAM characters. 9.5 Direct mode
Screen configuration
When DM = 0, the chip is not in the direct mode. Either the internal VLCD generator or an external voltage may be used to achieve VLCD. Table 9 Blink effect for icons and cursor character blink PARAMETER Cursor character blink Icons
EVEN PHASE block (all on) state 1; CGRAM character 0 to 2
ODD PHASE normal (display character) state 2; CGRAM character 4 to 6
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Philips Semiconductors
Product specification
LCD controllers/drivers
9.8 Bit P P = 0: default. P = 1: mirrors the column data. Bit Q Q = 0: default. Q = 1: mirrors the row data. 9.9 Temperature control Display configuration VLCD programming:
PCF2113X
1. Send `function set' instruction with H = 1 2. Send `set VLCD' instruction to write to voltage register: a) DB7, DB6 = 10: DB5 to DB0 are VLCD of character mode (VA) b) DB7, DB6 = 11: DB5 to DB0 are VLCD of icon mode (VB) c) DB5 to DB0 = 000000 switches VLCD generator off (when selected) d) During `display off' and power-down the VLCD generator is also disabled. 3. Send `function set' instruction with H = 0 to resume normal programming. 9.11 Reducing current consumption
Default is TC1 = 0 and TC2 = 0. Selects the default temperature coefficient for the internally generated VLCD (see Table 10). The ranges for TC are given in Chapter 13. Table 10 TC1 and TC2 selection of VLCD temperature coefficient TC1 0 1 0 1 9.10 TC2 0 0 1 1 Set VLCD DESCRIPTION VLCD temperature coefficient 0 VLCD temperature coefficient 1 VLCD temperature coefficient 2 VLCD temperature coefficient 3
Reducing current consumption can be achieved by one of the options given in Table 11. When VLCD lies outside the VDD range and must be generated, it is usually more efficient to use the on-chip generator than an external regulator. Table 11 Reducing current consumption ORIGINAL MODE Character mode Display on VLCD generator operating Any mode ALTERNATIVE MODE Icon mode (control bit IM) Display off (control bit D) Direct mode power-down (PD pin)
The VLCD value is programmed by instruction. Two on-chip registers, VA and VB hold VLCD values for the character mode and the icon mode respectively. The generated VLCD value is independent of VDD, allowing battery operation of the chip.
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Philips Semiconductors
Product specification
LCD controllers/drivers
10 INTERFACES TO MICROCONTROLLER 10.1 Parallel interface 10.2 I2C-bus interface
PCF2113X
The PCF2113X can send data in either two 4-bit operations or one 8-bit operation and can thus interface to 4-bit or 8-bit microcontrollers. In 8-bit mode data is transferred as 8-bit bytes using the 8 data lines DB7 to DB0. Three further control lines E, RS and R/W are required (see Chapter 6). In 4-bit mode data is transferred in two cycles of 4 bits each using pins DB7 to DB4 for the transaction. The higher order bits (corresponding to DB7 to DB4 in 8-bit mode) are sent in the first cycle and the lower order bits (DB3 to DB0 in 8-bit mode) in the second cycle. Data transfer is complete after two 4-bit data transfers. It should be noted that two cycles are also required for the busy flag check. 4-bit operation is selected by instruction, see Figs 17 to 19 for examples of bus protocol. In 4-bit mode, pins DB3 to DB0 must be left open-circuit. They are pulled up to VDD internally.
The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are the Serial Data line (SDA) and the Serial Clock Line (SCL). Both lines must be connected to a positive supply via pull-up resistors. Data transfer may be initiated only when the bus is not busy. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration).
RS
R/W
E
DB7
IR7
IR3
BF
AC3
DR7
DR3
DB6
IR6
IR2
AC6
AC2
DR6
DR2
DB5
IR5
IR1
AC5
AC1
DR5
DR1
DB4
IR4 instruction write
IR0
AC4
AC0
DR4
DR0
busy flag and address counter read
data register read
MGA804
Fig.17 4-bit transfer example.
2001 Dec 19
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2113X
RS
R/W
E
internal
internal operation
DB7
IR7
IR3
busy
AC3
not busy
AC3
D7
D3
instruction write
busy flag check
busy flag check
instruction write
MGA805
IR7, IR3: instruction 7th, 3rd bit. AC3: address counter 3rd bit. D7, D3: data 7th, 3rd bit.
Fig.18 An example of 4-bit data transfer timing sequence.
RS
R/W
E
internal
internal operation
DB7
data instruction write
busy busy flag check
busy busy flag check
not busy busy flag check
data instruction write
MGA806
Fig.19 Example of busy flag checking timing sequence.
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Philips Semiconductors
Product specification
LCD controllers/drivers
A master receiver must signal an end of data to the transmitter by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. 10.2.1 I2C-BUS PROTOCOL 10.2.2 DEFINITIONS
PCF2113X
* Transmitter: the device which sends the data to the bus * Receiver: the device which receives the data from the bus * Master: the device which initiates a transfer generates clock signals and terminates a transfer * Slave: the device addressed by a master * Multi-master: more than one master can attempt to control the bus at the same time without corrupting the message * Arbitration: procedure to ensure that if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted * Synchronization: procedure to synchronize the clock signals of two or more devices.
Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the START procedure. The I2C-bus configuration for the different PCF2113X read and write cycles is shown in Figs 24 to 26. The slow down feature of the I2C-bus protocol (receiver holds SCL LOW during internal operations) is not used in the PCF2113X.
MASTER TRANSMITTER/ RECEIVER SDA SCL
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
MGA807
Fig.20 System configuration.
handbook, full pagewidth
SDA
SCL data line stable; data valid change of data allowed
MBC621
Fig.21 Bit transfer.
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34
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2113X
handbook, full pagewidth
SDA
SDA
SCL S START condition P STOP condition
SCL
MBC622
Fig.22 Definition of START and STOP conditions.
handbook, full pagewidth
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition clock pulse for acknowledgement
MBC602
1
2
8
9
Fig.23 Acknowledgement on the I2C-bus.
2001 Dec 19
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acknowledgement from PCF2113X S
Philips Semiconductors
handbook, full pagewidth
LCD controllers/drivers
S 0 1 1 1 0 1 A 0 A 1 RS CONTROL BYTE A
0 2n 0 bytes
DATA BYTE
A 0 RS CONTROL BYTE A
DATA BYTE
AP
slave address R/W Co
1 byte Co
n 0 bytes update data pointer
MGG002
36
S 011101A0 0 PCF2113X slave address R/W
Product specification
PCF2113X
Fig.24 Master transmits to slave receiver; write mode.
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acknowledgement S
Philips Semiconductors
handbook, full pagewidth
LCD controllers/drivers
S 0 1 1 1 0 1 A 0 A 1 RS CONTROL BYTE A
0
DATA BYTE
A 0 RS CONTROL BYTE A
DATA BYTE(1)
A
slave address R/W Co
2n
0 bytes Co
1 byte
n 0 bytes
37
acknowledgement acknowledgement no acknowledgement
S
SLAVE ADDRESS
S A1A 0
DATA BYTE
A
DATA BYTE
1P
n bytes R/W Co update data pointer
last byte update data pointer
MGG003
Product specification
PCF2113X
Last data byte is a dummy byte (may be omitted).
Fig.25 Master reads after setting word address; writes word address, set RS; `read data'.
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2113X
handbook, full pagewidth
acknowledgement from PCF2113X
acknowledgement from master
no acknowledgement from master
S
SLAVE ADDRESS
S A1A 0
DATA BYTE
A
DATA BYTE
1P
n bytes R/W Co update data pointer
last byte update data pointer
MGG004
Fig.26 Master reads slave immediately after first byte; read mode (RS previously defined).
11 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDD1 VDD2, VDD3 VLCD Vi/o(n) PARAMETER logic supply voltage VLCD generator supply voltages LCD supply voltage voltage on any VDD related input or output any VLCD related input or output II IO Ptot PO Ves DC input current DC output current total power dissipation power dissipation per output electrostatic handling voltage electrostatic handling voltage Tstg storage temperature human body model; C = 100 pF; R = 1.5 k machine model; C = 200 pF; L = 0.75 H -0.5 -0.5 -10 -10 -50 - - - - -65 VDD + 0.5 +10 +10 +50 400 100 2000 150 +150 V mA mA mA mW mW V V C VLCD + 0.5 V CONDITIONS MIN. -0.5 -0.5 -0.5 +4 +6.5 MAX. +5.5 UNIT V V V
IDD, ISS and ILCD VDD, VSS or VLCD supply current
12 HANDLING INSTRUCTIONS Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see "Handling MOS Devices").
2001 Dec 19
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2113X
13 DC CHARACTERISTICS VDD1 = 1.8 to 5.5 V; VDD2 = VDD3 = 2.2 to 4.0 V; VSS = 0 V; VLCD = 2.2 to 6.5 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL Supplies VDD1 logic supply voltage note 1 internal VLCD generation (VDD2 and VDD3 < VLCD) note 1 and 2 1.8 2.2 2.2 0.9 - VDD = 3 V; VLCD = 5 V; note 4 icon mode; VDD = 3 V; VLCD = 2.5 V; note 4 - - - - - - 70 45 25 2 5.5 4.0 6.5 1.6 V V V V A A A A VDD2, VDD3 VLCD generator supply voltages VLCD VPOR ISS1 ISS3 ISS4 ISS5 LCD supply voltage Power-on reset voltage PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
GROUND SUPPLY CURRENT; EXTERNAL VLCD; note 3 ground supply current 1 ground supply current 3 ground supply current 4 ground supply current 5 120 80 45 5
- Power-down mode; VDD = 3 V; VLCD = 2.5 V; DB7 to DB0, RS and R/W = 1; OSC = 0; PD = 1 - VDD = 3 V; VLCD = 5 V; note 4 icon mode; VDD = 2.5 V; VLCD = 2.5 V; note 4 - -
GROUND SUPPLY CURRENT; INTERNAL VLCD; notes 3 and 5 ISS6 ISS8 ISS9 Logic VIL VIH VIL(OSC) VIH(OSC) IOL(DB) IOH(DB) Ipu IL LOW-level input voltage HIGH-level input voltage LOW-level input voltage on pin OSC HIGH-level voltage pin OSC LOW-level output current on pins DB7 to DB0 HIGH-level output current on pins DB7 to DB0 pull-up current at pins DB7 to DB0 leakage current VOL = 0.4 V; VDD1 = 5 V VOH = 4 V; VDD1 = 5 V VI = VSS1 VI = VDD1 or VSS1 VSS1 0.7VDD1 VSS1 VDD1 - 0.1 1.6 -1 0.04 -1 - - - - 4 -8 0.15 - 0.3VDD1 VDD1 V V ground supply current 6 ground supply current 8 ground supply current 9 190 160 120 400 400 - A A A
VDD1 - 1.2 V VDD1 - - 1 +1 V mA mA A A
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39
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2113X
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I2C-bus; pins SDA and SCL VIL VIH ILI Ci IOL (SDA) LOW-level input voltage HIGH-level input voltage input leakage current input capacitance LOW-level output current on pin SDA VI = VDD1 or VSS1 note 6 VOL = 0.4 V; VDD1 > 2 V VOL = 0.2 VDD1; VDD1 < 2 V note 7 note 7 note 8 Tamb = 25 C; note 5 VLCD < 3 V VLCD < 4 V VLCD < 5 V VLCD < 6 V TC0 TC1 TC2 TC3 Notes 1. Spikes on VDD1 or VSS1 which cause VDD1 - VSS1 1.6 V can cause a Power-on reset. 2. Resets all logic when VDD1 < VPOR; 3 OSC cycles required. 3. LCD outputs are open-circuit; inputs at VDD1 or VSS1; bus inactive. 4. Tamb = 25 C; fOSC = 200 kHz. 5. LCD outputs are open-circuit; VLCD generator is on; load current IVLCD = 5 A (at VLCD). 6. Tested on sample basis. 7. Resistance of output pins (R1 to R18 and C1 to C60) with a load current of 10 A; outputs measured one at a time; external VLCD = 3 V, VDD1, 2, 3 = 3 V. 8. LCD outputs open-circuit; external VLCD. VLCD temperature coefficient 0 VLCD temperature coefficient 1 VLCD temperature coefficient 2 VLCD temperature coefficient 3 - - - - - - - - - - - - -0.16 -0.18 -0.21 -0.24 160 200 260 340 - - - - mV mV mV mV %/K %/K %/K %/K 0 0.7VDD1 -1 - 3 2 - - - - - - 5 - - 10 15 20 0.3VDD1 5.5 +1 - - - 30 40 130 V V A pF mA mA
LCD outputs RO(ROW) RO(COL) Vbias(tol) VLCD2(tol) row output resistance of pins R1 to R18 column output resistance of pins C1 to C60 bias voltage tolerance on pins R1 to R18 and C1 to C60 VLCD voltage tolerance k k mV
2001 Dec 19
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2113X
14 AC CHARACTERISTICS VDD1 = 1.8 to 5.5 V; VDD2 = VDD3 = 2.2 to 4.0 V; VSS = 0 V; VLCD = 2.2 to 6.5 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL fFR fosc fOSC(ext) tosc(st) tW(PD) tSW(PD) PARAMETER LCD frame frequency (internal clock) oscillator frequency (not available at any pin) external clock frequency oscillator start-up time after power-down power-down HIGH-level pulse width tolerable spike width on PD pin note 1 note 1 CONDITIONS VDD = 5.0 V 45 140 140 - 1 - MIN. TYP. 95 250 - 200 - - MAX. 147 450 450 300 - 90 UNIT Hz kHz kHz s s ns
Timing characteristics of parallel interface; note 2 WRITE OPERATION (WRITING DATA FROM MICROCONTROLLER TO PCF2113X); see Fig.27 Tcy(en) tW(en) tsu(A) th(A) tsu(D) th(D) Tcy(en) tW(en) tsu(A) th(A) td(D) th(D) enable cycle time enable pulse width address set-up time address hold time data set-up time data hold time 500 220 50 25 60 25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 150 250 100 ns ns ns ns ns ns
READ OPERATION (READING DATA FROM PCF2113X TO MICROCONTROLLER); see Fig.28 enable cycle time enable pulse width address set-up time address hold time data delay time data hold time VDD1 > 2.2 V VDD1 > 1.5 V Timing characteristics of I2C-bus interface; see Fig.29; note 2 fSCL tLOW tHIGH tSU;DAT tHD;DAT tr tf Cb tSU;STA tHD;STA SCL clock frequency SCL clock LOW period SCL clock HIGH period data set-up time data hold time SCL and SDA rise time SCL and SDA fall time capacitive bus line load set-up time for a repeated START condition START condition hold time note 1 and 3 note 1 and 3 - 1.3 0.6 100 0 15 + 0.1 Cb 15 + 0.1 Cb - 0.6 0.6 400 - - - - 300 300 400 - - kHz s s ns ns ns ns pF s s 500 220 50 25 - - 5 ns ns ns ns ns ns ns
2001 Dec 19
41
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2113X
SYMBOL tSU;STO tSW tBUF Notes 1. Tested on sample base.
PARAMETER set-up time for STOP condition tolerable spike width on bus bus free time between STOP and START condition
CONDITIONS 0.6 - 1.3
MIN. - - -
TYP. -
MAX. 50 -
UNIT s ns s
2. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. 3. Cb = total capacitance of one bus line in pF.
handbook, full pagewidth
RS
VIH1 V IL1 t su(A)
VIH1 VIL1 t h(A)
R/W
V IL1 tW(en)
VIL1 t h(A) VIL1 t h(D) VIH1 VIL1
MBK474
E
VIH1 VIL1
VIH1 VIL1 t su(D)
DB0 to DB7
VIH1 valid data VIL1 Tcy(en)
Fig.27 Parallel bus write operation sequence; writing data from microcontroller to PCF2113X.
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42
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2113X
handbook, full pagewidth
RS
VIH1 V IL1 tsu(A)
VIH1 VIL1 t h(A) VIH1
R/W
VIH1
tW(en) E VIL1 VIH1 VIH1
t h(A) VIL1 VIL1
t d(D) DB0 to DB7 VOH1 VOL1 Tcy(en)
t h(D) VOH1 VOL1
MBK475
Fig.28 Parallel bus read operation sequence; writing data from PCF2113X to microcontroller.
handbook, full pagewidth
SDA
t BUF
t LOW
tf
SCL
t HD;STA
tr
t HD;DAT
t HIGH
t SU;DAT
SDA t SU;STA
MGA728
t
SU;STO
Fig.29 I2C-bus timing diagram.
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Philips Semiconductors
Product specification
LCD controllers/drivers
15 DEVICE PROTECTION CIRCUITS SYMBOL VDD1 PAD 1
VDD1
PCF2113X
INTERNAL CIRCUIT
VSS1
MGU200
VDD2
109
VDD2
VSS1 VSS2
MGU201
VDD3
110
VDD3
VSS1
MGU202
VSS1 VSS2
7 8
8 VSS2
7
VSS1
MGU203
VLCDSENSE VLCD1 VLCD2
10 11 9
VSS1
MGU196
SCL SDA
96 97
VDD1
VSS1
MGU198
2001 Dec 19
44
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2113X
SYMBOL OSC PD T1 T2 T3 E RS R/W DB0 to DB7 R1 to R8 R9 to R16 R17 R18 C1 to C2 C3 to 27 C28 to C52 C53 to C60
PAD 2 3 5 6 4 98 99 100 108 to 101 94 to 87 12 to 19 95 20 86 to 85 82 to 58 55 to 31 28 to 21
INTERNAL CIRCUIT
VDD1
VSS1
MGU199
VLCD2
VSS1
MGU197
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Philips Semiconductors
Product specification
LCD controllers/drivers
16 APPLICATION INFORMATION
PCF2113X
handbook, full pagewidth
P10 P11 P80CL51 P12
RS R/W E
R17, R18
2
R1 to R16 PCF2113X 16
2 x 12 CHARACTER LCD DISPLAY PLUS 120 ICONS 60
MGG006
P17 to P14
4
DB7 to DB4
C1 to C60
Fig.30 Direct connection to 8-bit microcontroller; 4-bit bus.
handbook, full pagewidth
P20 P21 P80CL51 P22
RS R/W E
R17, R18
2
R1 to R16 PCF2113X 16
2 x 12 CHARACTER LCD DISPLAY PLUS 120 ICONS 60
MGG005
P17 to P10
8
DB7 to DB0
C1 to C60
Fig.31 Direct connection to 8-bit microcontroller; 8-bit bus.
handbook, full pagewidth
OSC VDD
R17, R18
2
VDD R1 to R16 PCF2113X 100 nF VLCD 100 nF VSS C1 to C60 16
2 x 12 CHARACTER LCD DISPLAY PLUS 120 ICONS 60
VSS
8 DB7 to DB0 E RS R/W
MGG007
Fig.32 Typical application using parallel interface.
2001 Dec 19
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2113X
handbook, full pagewidth
VDD VDD
VDD
OSC VDD
DB3/SAO
R17, R18
2
VDD R1 to R16 PCF2113X 16
100 nF VSS
VLCD 100 nF VSS SCL SDA C1 to C60
2 x 12 CHARACTER LCD DISPLAY PLUS 120 ICONS 60
VSS
OSC VDD
DB3/SAO
R17, R18
2
VDD R1 to R16 PCF2113X 16
470 nF VSS
VLCD 100 nF VSS SCL SDA C1 to C60
1 x 24 CHARACTER LCD DISPLAY PLUS 120 ICONS 60
SCL SDA
MASTER TRANSMITTER PCF84C81A; P80CL410
MGG008
Fig.33 Application using I2C-bus interface.
16.1
General application information
The required minimum value for the external capacitors in an application with the PCF2113X are: CExt for VLCD/VSS = 100 nF min., for VDD/VSS = 470 nF. Higher capacitor values are recommended for ripple reduction. For COG applications the recommended ITO track resistance is to be minimized for the I/O and supply connections.
Optimized values for these tracks are below 50 for the supply and below 100 for the I/O connections. Higher track resistance reduce performance and increase current consumption. To avoid accidental triggering of Power-on reset (especially in COG applications), the supplies must be adequately decoupled. Depending on power supply quality, VDD1 may have to be risen above the specified minimum.
2001 Dec 19
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Philips Semiconductors
Product specification
LCD controllers/drivers
16.2 4-bit operation, 1-line display using internal reset 16.4 8-bit operation, 2-line display
PCF2113X
The program must set functions prior to a 4-bit operation (see Table 12). When power is turned on, 8-bit operation is automatically selected and the PCF2113X attempts to perform the first write as an 8-bit operation. Since nothing is connected to DB0 to DB3, a rewrite is then required. However, since one operation is completed in two accesses of 4-bit operation, a rewrite is required to set the functions (see Table 12 step 3). Thus, DB4 to DB7 of the `function set' are written twice. 16.3 8-bit operation, 1-line display using internal reset
For a 2-line display the cursor automatically moves from the first to the second line after the 40th digit of the first line has been written. Thus, if there are only 8 characters in the first line, the DDRAM address must be set after the 8th character is completed (see Table 15). It should be noted that both lines of the display are always shifted together; data does not shift from one line to the other. 16.5 I2C-bus operation, 1-line display
A control byte is required with most commands (see Table 16).
Tables 13 and 14 show an example of a 1-line display in 8-bit operation. The PCF2113X functions must be set by the `function set' instruction prior to display. Since the DDRAM can store data for 80 characters, the RAM can be used for advertising displays when combined with display shift operation. Since the display shift operation changes display position only and the DDRAM contents remain unchanged, display data entered first can be displayed when the `return home' operation is performed. Table 12 4-bit operation, 1-line display example using internal reset STEP 1 2 INSTRUCTION power supply on (PCF2113X is initialized by the internal reset) function set RS 0 3 R/W 0 DB7 0 DB6 0 DB5 1 DB4 0 sets to 4-bit operation; in this instance operation is handled as 8-bits by initialization and only this instruction completes with one write sets to 4-bit operation, selects 1-line display and VLCD = V0; 4-bit operation starts from this point and resetting is needed _ turns on display and cursor; entire display is blank after initialization DISPLAY OPERATION initialized; no display appears
function set 0 0 0 0 0 0 0 0 1 0 0 0
4
display control 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 0 0 0 _
5
entry mode set 0 0 sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the DD/CGRAM; display is not shifted writes `P'; the DDRAM has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right
6
`write data' to CGRAM/DDRAM 1 1 0 0 0 0 1 0 0 0 1 0 P_
2001 Dec 19
48
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LCD controllers/drivers
STEP 1 2
INSTRUCTION power supply on (PCF2113X is initialized by the internal reset) function set RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 1 0 0 _
DISPLAY
OPERATION initialized; no display appears
sets to 8-bit operation, selects 1-line display and VLCD = V0 turns on display and cursor; entire display is blank after initialization sets mode to increment the address by 1 and to shift the cursor to the right at the time of the write to the DD/CGRAM; display is not shifted writes `P'; the DDRAM has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right writes `H' writes `ILIP'
3
display control 0
4
entry mode set 0 0 0 0 0 0 0 1 1 0 _
5
`write data' to CGRAM/DDRAM 1 0 0 1 0 1 0 0 0 0 P_
6 7 to 10
`write data' to CGRAM/DDRAM 1 0 0 1 0 | | 0 1 0 0 0 PH_
11 12 13 14 15 to 19
`write data' to CGRAM/DDRAM 1 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 | | 1 0 0 0 0 0 0 1 0 1 0 1 1 1 0 0 1 1 0 1 PHILIPS_ PHILIPS_ HILIPS _ ILIPS M_ writes `S' sets mode for display shift at the time of write writes space Product specification writes `M' writes `ICROK' entry mode set `write data' to CGRAM/DDRAM `write data' to CGRAM/DDRAM
PCF2113X
20
`write data' to CGRAM/DDRAM 1 0 0 1 0 0 1 1 1 1 MICROKO_ writes `O'
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LCD controllers/drivers PCF2113X
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 14 8-bit operation, 1-line display and icon example; using internal reset (character set `A') 2001 Dec 19 51 Philips Semiconductors
LCD controllers/drivers
STEP 1 2
INSTRUCTION power supply on (PCF2113X is initialized by the internal reset) function set RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 1 0 0 _
DISPLAY
OPERATION initialized; no display appears
sets to 8-bit operation, selects 1-line display and VLCD = V0 turns on display and cursor; entire display is blank after initialization sets mode to increment the address by 1 and to shift the cursor to the right at the time of the write to the DD/CGRAM; display is not shifted sets the CGRAM address to position of character 0; the CGRAM is selected writes data to CGRAM for icon even phase; icons appears
3
display mode on/off control 0
4
entry mode set 0 0 0 0 0 0 0 1 1 0 _
5
set CGRAM address 0 0 0 1 0 0 0 0 0 0 _
6 7
`write data' to CGRAM/DDRAM 1 0 0 0 0 | | 0 1 0 1 0 _
8
set CGRAM address 0 0 0 1 1 1 0 0 0 0 _ sets the CGRAM address to position of character 4; the CGRAM is selected writes data to CGRAM for icon odd phase
9 10
`write data' to CGRAM/DDRAM 1 0 0 0 0 | | 0 1 0 1 0 _
11 12 13
function set
Product specification
PCF2113X
0 0 0
0 0 0
0 0 0
0 0 0
1 0 1
1 0 1
0 1 0
0 0 0
0 1 0
1 0 1
_ _ _
sets H = 1 icons blink sets H = 0
icon control function set
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2001 Dec 19 52 Product specification Philips Semiconductors STEP 14 set DDRAM address 0 15 0 1 0 0 0 0 0 0 0 sets the DDRAM address to the first position; DDRAM is selected P_ writes `P'; the cursor is incremented by 1 and shifted to the right writes `H' writes `ILIPS' INSTRUCTION DISPLAY OPERATION
LCD controllers/drivers
`write data' to CGRAM/DDRAM 1 0 0 1 0 1 0 0 0 0
16 17 to 21
`write data' to CGRAM/DDRAM 1 0 0 1 0 | | 0 1 0 0 0 PH_
22
return home 0 0 0 0 0 0 0 0 1 0 PHILIPS returns both display and cursor to the original position (address 0)
PCF2113X
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 15 8-bit operation, 2-line display example; using internal reset 2001 Dec 19 53 Philips Semiconductors
LCD controllers/drivers
STEP 1 2
INSTRUCTION power supply on (PCF2113X is initialized by the internal reset) function set RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 1 0 0 _
DISPLAY
OPERATION initialized; no display appears
sets to 8-bit operation; selects 2-line display and VLCD generator off
3
display on/off control 0 turns on display and cursor; entire display is blank after initialization sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the CG/DDRAM; display is not shifted writes `P'; the DDRAM has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right writes `HILIP'
4
entry mode set 0 0 0 0 0 0 0 1 1 0 _
5
`write data' to CGRAM/DDRAM 1 0 0 1 0 1 0 0 0 0 P_
6 to 10
| |
11 12
`write data' to CGRAM/DDRAM 1 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 1 0 1 0 PHILIPS_ PHILIPS _ PHILIPS M_ writes `S' sets DDRAM address to position the cursor at the head of the 2nd line writes `M' writes `ICROC' Product specification set DDRAM address
13
`write data' to CGRAM/ DDRAM 1 0 0 1 0 | | 0 1 1 0 1
14 to 18
PCF2113X
19
`write data' to CGRAM/DDRAM 1 0 0 1 0 0 1 1 1 1 PHILIPS MICROCO_ writes `O'
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LCD controllers/drivers
`write data' to CGRAM/DDRAM 1 0 0 1 0 0 1 1 0 1 writes `M'; display is shifted to the left; the first and second lines shift together returns both display and cursor to the original position (address 0)
23
return home 0 0 0 0 0 0 0 0 1 0
PCF2113X
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 16 Example of I2C-bus operation; 1-line display (using internal reset, assuming SA0 = VSS; note 1) STEP 1 2 I2C-bus start I2C-BUS BYTE slave address for write SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack 0 3 Co 0 4 1 RS 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 Ack 1 selects 1-line display and VLCD = V0; SCL pulse during acknowledge cycle starts execution of instruction send a control byte for `function set' control byte sets RS for following data bytes during the acknowledge cycle SDA will be pulled-down by the PCF2113X DISPLAY OPERATION initialized; no display appears 2001 Dec 19 55 7 8 9 10 11 Philips Semiconductors
LCD controllers/drivers
function set DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 1 X 0 0 0 0 1 _
5
display on/off control DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 0 0 1 1 1 0 1 _ turns on display and cursor; entire display shows character 20H (blank in ASCII-like character sets)
6
entry mode set DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 0 0 0 1 1 0 1 _ sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the DDRAM or CGRAM; display is not shifted for writing data to DDRAM, RS must be set to 1; therefore a control byte is needed
I2C-bus start slave address for write SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack 0 Co 0 1 RS 1 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 Ack 1 send a control byte for `write data'
_
_
`write data' to DDRAM Product specification DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 1 0 0 0 0 1 PH_ `write data' to DDRAM DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 0 1 0 0 0 1 writes `H' P_ writes `P'; the DDRAM has been selected at power-up; the cursor is incremented by 1 and shifted to the right
PCF2113X
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2001 Dec 19 56 Philips Semiconductors STEP 12 to 15 I2C-BUS BYTE | | 16 `write data' to DDRAM DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 17 18 1 0 1 0 0 1 1 1 PHILIPS_ (optional I2C-bus stop) I2C-bus start start + slave address for write (as step 8) control byte Co 1 19 RS 0 0 0 0 0 0 0 0 0 0 0 0 0 Ack 1 PHILIPS sets DDRAM address 0 in address counter (also returns shifted display to original position; DDRAM contents unchanged); this instruction does not update the Data Register (DR) PHILIPS_ PHILIPS_ writes `S' DISPLAY OPERATION
LCD controllers/drivers
return home DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 0 0 0 0 1 0 1 PHILIPS PHILIPS during the acknowledge cycle the content of the DR is loaded into the internal I2C-bus interface to be shifted out; in the previous instruction neither a `set address' nor a `read data' has been performed; therefore the content of the DR was unknown; the R/W has to be set to 1 while still in I2C-write mode DDRAM content will be read from following instructions
20 21
I2C-bus start slave address for read SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack 0 1 1 1 0 1 0 1 1
22
control byte for read Co 0 RS 1 0 1 0 0 0 0 0 0 0 0 0 0 Ack 1 PHILIPS 8 x SCL; content loaded into interface during previous acknowledge cycle is shifted out over SDA; MSB is DB7; during master acknowledge content of DDRAM address 01 is loaded into the I2C-bus interface PHILIPS
23
`read data': 8 x SCL + master acknowledge; note 2 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack X X X X X X X X 0
Product specification
PCF2113X
24
`read data': 8 x SCL + master acknowledge; note 2 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 0 1 0 0 0 0 PHILIPS 8 x SCL; code of letter `H' is read first; during master acknowledge code of `I' is loaded into the I2C-bus interface
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LCD controllers/drivers
26 Notes
I2C-bus stop
PHILIPS
1. X = don't care. 2. SDA is left at high-impedance by the microcontroller during the read acknowledge.
PCF2113X
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 17 Initialization by instruction, 8-bit interface (note 1) 2001 Dec 19 58 Philips Semiconductors
LCD controllers/drivers
STEP power-on or unknown state | wait 2 ms after internal reset has been applied | RS 0 R/W 0 DB7 0 DB6 0 DB5 1 | wait 2 ms | RS 0 R/W 0 DB7 0 DB6 0 DB5 1 | wait more than 40 s | RS 0 R/W 0 DB7 0 DB6 0 DB5 1 | | RS 0 0 0 0 R/W 0 0 0 0 DB7 0 0 0 0 DB6 0 0 0 0 DB5 1 0 0 0 | Initialization ends DB4 1 0 0 0 DB3 0 1 0 0 DB2 M 0 0 1 DB1 0 0 0 I/D DB0 H 0 1 S display off clear display entry mode set DB4 1 DB3 X DB2 X DB1 X DB0 X DB4 1 DB3 X DB2 X DB1 X DB0 X DB4 1 DB3 X DB2 X DB1 X DB0 X
DESCRIPTION
BF cannot be checked before this instruction function set (interface is 8 bits long)
BF cannot be checked before this instruction function set (interface is 8 bits long)
BF cannot be checked before this instruction function set (interface is 8 bits long) BF can be checked after the following instructions; when BF is not checked, the waiting time between instructions is the specified instruction time (see Table 3) function set (interface is 8 bits long); specify the number of display lines
Product specification
Note 1. X = don't care.
PCF2113X
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LCD controllers/drivers
STEP power-on or unknown state | Wait 2 ms after internal reset has been applied | RS 0 R/W 0 DB7 0 | Wait 2 ms | RS 0 R/W 0 DB7 0 | Wait 40 s | RS 0 R/W 0 DB7 0 | RS 0 0 0 0 0 0 0 0 0 R/W 0 0 0 0 0 0 0 0 0 DB7 0 0 0 0 1 0 0 0 0 | Initialization ends DB6 0 0 M 0 0 0 0 0 1 DB5 1 1 0 0 0 0 0 0 I/D DB4 0 0 H 0 0 0 1 0 S entry mode set display off clear display DB6 0 DB5 1 DB4 1 DB6 0 DB5 1 DB4 1 DB6 0 DB5 1 DB4 1
DESCRIPTION
BF cannot be checked before this instruction function set (interface is 8 bits long)
BF cannot be checked before this instruction function set (interface is 8 bits long)
BF cannot be checked before this instruction function set (interface is 8 bits long) BF can be checked after the following instructions; when BF is not checked, the waiting time between instructions is the specified instruction time (see Table 3) function set (set interface to 4 bits long) interface is 8 bits long function set (interface is 4 bits long) specify number of display lines
Product specification
PCF2113X
Philips Semiconductors
Product specification
LCD controllers/drivers
17 BONDING PAD INFORMATION SYMBOL VDD1 OSC PD T3 T1 T2 VSS1 VSS2 VLCD2 VLCDSENSE VLCD1 R9 R10 R11 R12 R13 R14 R15 R16 R18 C60 C59 C58 C57 C56 C55 C54 C53 dummy pad 1 dummy pad 2 C52 C51 C50 C49 C48 C47 C46 C45 C44 C43 C42 C41 2001 Dec 19 PAD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 COORDINATES(1) X -1345 -1155 -1 055 -845 -765 -665 -525 -455 -295 -145 +15 +175 +245 +315 +385 +455 +525 +595 +665 +735 +805 +875 +995 +1065 +1135 +1205 +1275 +1345 +1435 +1630 +1630 +1630 +1630 +1630 +1630 +1630 +1630 +1630 +1630 +1630 +1630 +1630 Y -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1395 -1255 -1155 -1055 -955 -735 -635 -535 -435 -335 -235 -135 -35 60 SYMBOL C40 C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28 dummy pad 3 dummy pad 4 C27 C26 C25 C24 C23 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 dummy pad 5 dummy pad 6 C2 PAD 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85
PCF2113X
COORDINATES(1) X +1630 +1630 +1630 +1630 +1630 +1630 +1630 +1630 +1630 +1630 +1630 +1630 +1630 +1630 +1435 +1335 +1225 +1115 +1005 +765 +665 +565 +465 +365 +265 +165 +65 -35 -135 -235 -335 -435 -535 -635 -735 -835 -965 -1065 -1165 -1265 -1465 -1630 -1630 Y +65 +165 +265 +365 +465 +565 +665 +765 +865 +965 +1065 +1165 +1265 +1335 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1355 +1255
Philips Semiconductors
Product specification
LCD controllers/drivers
COORDINATES(1) X -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 Y +1185 +1115 +1045 +975 +905 +835 +765 +695 +625 +555 +375 +305 +85 -15 -115
PCF2113X
COORDINATES(1) X -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1465 Y -215 -315 -415 -515 -615 -715 -815 -915 -1015 -1235 -1395 -1550
SYMBOL C1 R8 R7 R6 R5 R4 R3 R2 R1 R17 SCL SDA E RS R/W
PAD 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
SYMBOL DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VDD2 VDD3 dummy pad 7 dummy pad 8 Note
PAD 101 102 103 104 105 106 107 108 109 110 111 112
1. All x and y coordinates are referenced to centre of chip and dimensions are in m (see Fig.34).
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2113X
dummy pad 5
handbook, full pagewidth
71
81
78
77
76
75
74
73
72
70
69
68
67
66
65
64
63
62
61
60
59
58
83
82
80
79
dummy pad 6 C2 C1 R8 R7 R6 R5 R4 R3 R2 R1 R17 SCL SDA
E
84 85 86 87 88 89 90 91 92 93 94 95
y
57
dummy pad 4
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C3
C4
C5
C6
C7
C8
C9
56 55 54 53 52 51 50 49
dummy pad 3 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 dummy pad 2
PC2113x
48 47
96 97
46 45 44
3.36 mm
98 99 100 101 102 103 104 105 106 107 108 109
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VDD2 VDD3 dummy pad 7
x 0 0
43 42 41 40 39 38 37 36 35
34 33 32
110 111
112 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 10 29 1 2 3 4 5 6 7 8 9
31 30
OSC PD
T3 T1
T2
VSS1 VSS2
VLCDSENSE
R9 R10 R11 R12 R13 R14 R15 R16 R18 C60 C59
3.52 mm
MGU205
Fig.34 Bonding pad locations.
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C58 C57 C56 C55 C54 C53 dummy pad 1
dummy pad 8
VDD1
VLCD2
VLCD1
Philips Semiconductors
Product specification
LCD controllers/drivers
18 TRAY INFORMATION
handbook, full pagewidth
PCF2113X
x
A
C
y D
B F
E
MGU206
For dimensions see Table 19.
Fig.35 Tray details.
Table 19 Tray dimensions DIMENSION A B
handbook, halfpage
DESCRIPTION pocket pitch x direction pocket pitch y direction pocket width x direction pocket width y direction tray width x direction tray width y direction pockets in x direction pockets in y direction
VALUE 6.35 mm 5.59 mm 3.82 mm 3.66 mm 50.8 mm 50.8 mm 7 8
C D E F x
PC2113x
y
Table 20 Bump size PARAMETER
MGU207
VALUE galvanic pure Au 50 6 90 6 17.5 5 <2 <5 62 x 100 36 x 76 380 25
UNIT - m m m m m m m m
The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to the bonding pad location diagram for the orientating and position of the type name on the die surface.
Fig.36 Tray alignment.
Type Bump width Bump length Bump height Height difference in one die Convex deformation Pad size, aluminium Passivation opening CBB Wafer thickness 63
2001 Dec 19
Philips Semiconductors
Product specification
LCD controllers/drivers
19 PACKAGE OUTLINE LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
PCF2113X
SOT407-1
c
y X 75 76 51 50 ZE A
e E HE wM bp L pin 1 index 100 1 ZD bp D HD wM B vM B 25 vM A 26 detail X Lp A A2 (A 3)
A1
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 14.1 13.9 E (1) 14.1 13.9 e 0.5 HD HE L 1.0 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 Z D (1) Z E (1) 1.15 0.85 1.15 0.85 7 0o
o
16.25 16.25 15.75 15.75
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT407-1 REFERENCES IEC 136E20 JEDEC MS-026 EIAJ EUROPEAN PROJECTION
ISSUE DATE 00-01-19 00-02-01
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Product specification
LCD controllers/drivers
20 SOLDERING 20.1 Introduction to soldering surface mount packages
PCF2113X
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 20.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 20.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. 20.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Product specification
LCD controllers/drivers
20.5 Suitability of surface mount IC packages for wave and reflow soldering methods
PCF2113X
SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable
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Product specification
LCD controllers/drivers
21 DATA SHEET STATUS DATA SHEET STATUS Objective specification PRODUCT STATUS Development DEFINITIONS (1)
PCF2113X
This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Preliminary specification
Qualification
Product specification
Production
Note 1. Please consult the most recently issued data sheet before initiating or completing a design. 22 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 24 BARE DIE DISCLAIMER All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post packing tests performed on individual die or wafer. Philips Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, Philips Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. 23 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
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Philips Semiconductors
Product specification
LCD controllers/drivers
25 PURCHASE OF PHILIPS I2C COMPONENTS
PCF2113X
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
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Philips Semiconductors
Product specification
LCD controllers/drivers
NOTES
PCF2113X
2001 Dec 19
69
Philips Semiconductors
Product specification
LCD controllers/drivers
NOTES
PCF2113X
2001 Dec 19
70
Philips Semiconductors
Product specification
LCD controllers/drivers
NOTES
PCF2113X
2001 Dec 19
71
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2001
SCA73
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
403502/03/pp72
Date of release: 2001
Dec 19
Document order number:
9397 750 06995

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